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230 Part 3 The instruction-set processor level: variations in the processor

Section 3 Processors for variable-length-string data

Fig. 5. IBM 1401 system data flow (registers structure). (Courtesy of International Business

Machines Corporation.)

transfer level primitives of the complete computer together with several options. The options, of course, increase the complexity (and concurrency). Without the overlap feature, for example, all data are accessed in Mp via Pc's address registers.

There are register pairs consisting of a 3-character memory address (access) register, and a 1-character data register. The memory-address, memory-data register pairs are A_ address, A_ data; B_ address, B_ data; I_ address, Operation/Op; Overlap_ address, Overlap_ data/O.

The implementation is straightforward, and the instruction times (Table 2) show the implementation at the register-transfer level. For example, as an instruction is being read by Pc, prior to instruction execution, each new character is taken in and examined for the instruction-terminating flag bit. When the flag bit is present, the instruction is complete and ready to be executed. The character of the next instruction is not saved but is picked up again after the previous instruction has been executed.

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